The present invention relates to a data demultiplexer adapted for reproducing time-division multiplex data recorded on an optical disk or the like and separating the same into video data and audio data.
FIG. 5 is a block diagram showing an exemplary constitution of a conventional data demultiplexer known heretofore. In this diagram, a drive 1 reproduces the data recorded on an optical disk incorporated therein. On this optical disk, there are recorded both video data and audio data in a time-division multiplex form. The reproduced data outputted from the drive 1 is supplied to a demodulator 2 so as to be demodulated. An ECC circuit 3 detects and corrects any error in the data outputted from the demodulator 2 and supplies the processed data to a ring buffer 4. Then the ring buffer 4 stores a predetermined amount of the supplied data therein and subsequently outputs the data to a data demultiplexer 5.
The data demultiplexer 5 has a data separation circuit 21 which demultiplexes the data supplied from the ring buffer 4 to thereby separate the same into video data and audio data, and further into timing data such as SCR (system clock reference) and DTS (decoding time stamp) inclusive of DTSV for the video data and DTSA for the audio data.
The format of the data supplied to the data demultiplexer 5 is so standardized as shown in FIG. 6 for example. This format is prescribed as a multiplex bit stream in the MPEG (ISO11172). As shown in FIG. 6, a multiplex bit stream is composed of one or more packs (PACKS), each of which is composed of one or more packets (PACKETS). A pack header (PACK HEADER) is disposed at the top of each pack and has a pack start code (PACK START CODE) indicating a start point of the pack, and also SCR and MUX.sub.-- RATE. This SCR indicates the time when the last byte is inputted to the data demultiplexer 5 (the time when demultiplexing is started), and the MUX.sub.-- RATE signifies a transfer rate.
In the example of FIG. 6, a video packet (VIDEO PACKET) and an audio packet (AUDIO PACKET) are disposed next to the pack header. A packet header is disposed at the top of each of such packets and has a video packet start code (VIDEO PACKET START CODE) or an audio packet start code (AUDIO PACKET START CODE) indicating a start point of the video or audio packet, and further has DTSV or DTSA indicating a decoding start time of the video or audio data. Video data or audio data is disposed next to each packet header. However, since the amount of video data per unit time is greater than that of audio data, video timing data DTSV is disposed at a rate of once per plural packs.
Such timing data of SCR and DTS (DTSV or DTSA) are represented by count values of 90-kHz clock pulses and have 33-bit effective digits.
The video data is supplied to a video code buffer 6 (FIFO). Meanwhile the audio data is supplied to an audio code buffer 8 (FIFO). The reference timing data SCR is supplied to an STC register 26 to be stored therein. The STC register 26 counts 90-kHz clock pulses outputted from a clock generator 27 and increments its storage value to generate an STC (system time clock) signal.
The timing data DTSV and DTSA are supplied to a DTSV register 22 and a DTSA register 24 respectively so as to be stored therein. The timing data thus stored in the DTSV register 22 and the DTSA register 24 are supplied to comparators 23 and 25 respectively so as to be compared with the STC signal outputted from the STC register 26. A control circuit 28 consists of a CPU or the like and serves to control the data separation circuit 21 in response to a command received from an input unit 29 by a user's manipulation.
The video data stored in the video code buffer 6 is read out therefrom and is supplied to a video decoder 7. Then, the video data is decoded to become a video signal, which is subsequently outputted to an unshown circuit. To the video decoder 7, there is also supplied a video decoding start signal which is outputted from the comparator 23.
Similarly, the data outputted from the audio code buffer 8 is supplied to an audio decoder 9 so as to be decoded. To the audio decoder 9, there is also supplied the output of the comparator 25 as an audio decoding start signal.
Now the operation will be described below with reference to a timing chart of FIG. 7. First, the input unit 29 is manipulated for instructing the control circuit 28 to start reproduction. Then, the control circuit 28 sends a command to the drive 1 to thereby reproduce the data recorded on an optical disk incorporated in the drive 1. The reproduced data outputted from the drive 1 is supplied to the demodulator 2, and the demodulated data obtained therefrom is supplied to the ECC circuit 3 where a process of error detection and correction is executed. The data thus processed is supplied via the ring buffer 4 to the data separation circuit 21 in the data demultiplexer 5.
The data separation circuit 21 is controlled by the control circuit 28 and separates the output data of the ring buffer 4 into video data and audio data, which are then supplied to the video code buffer 6 and the audio code buffer 8, respectively. The circuit 21 further separates the timing data into SCR, DTSV and DTSA, which are supplied respectively to the STC register 26, the DTSV register 22 and the DTSA register 24 and then are stored therein.
The STC register 26 having stored the timing data SCR therein counts the clock pulses outputted from the clock generator 27 and increments the storage value in response to the clock pulses. The storage value of the STC register 26 is supplied as a system time clock (STC) signal to the comparators 23 and 25.
The DTSV register 22 holds the video timing data DTSV supplied first thereto after the start of reproduction by the drive 1. Consequently, the register 22 has a decoding start time relative to a top picture out of the entire data stored in the video code buffer 6.
Similarly, the DTSA register 24 holds the audio timing data DTSA supplied first thereto after the start of reproduction, so that the register 24 has a decoding start time relative to a top decode unit out of the entire data stored in the audio code buffer 8.
The reference timing data SCR corresponds to the time when demultiplexing is started after supply of the data from the ring buffer 4 to the data demultiplexer 5. More specifically, it corresponds to a time t1 in the timing chart of FIG. 7. Therefore the STC register 26 outputs the time data (current time) from the time t1 to one input terminal of each of the comparators 23 and 25.
The DTSV register 22 supplies the video timing data DTSV, which indicates the decoding start time of the video decoder 7, to the other input terminal of the comparator 23. When the current time outputted from the STC register 26 has become coincident with the decoding start time outputted from the DTSV register 22 (i.e., at a time t2 in FIG. 7), the comparator 23 outputs a video decoding start signal to the video decoder 7. In response to the video decoding start signal thus received, the video decoder 7 reads out one frame of the video data written in the video code buffer 6 and then starts its decoding.
In FIG. 7, a straight line A represents a state of writing the data in the video code buffer 6 (with an inclination signifying a write and transfer rate), and a line B represents a state of reading out the data from the video code buffer 6 by the video decoder 7. It follows, therefore, that the data within a shaded area in FIG. 7 is left in the video code buffer 6. The storage capacity of the video code buffer 6 is expressed by a distance perpendicular to the time axis extending from line A to a line C.
The video decoder 7 starts its decoding in response to the video decoding start signal supplied thereto and generates a video vertical synchronizing signal upon completion of the decoding, i.e., after a lapse of a video decode delay (VIDEO-DECODE-DELAY) from the start of the decoding, and then outputs a video signal in succession thereto. More specifically, a display is started after a lapse of the video decode delay from the start of the decoding.
Similarly, the comparator 25 outputs an audio decoding start signal when the current time outputted from the STC register 26 has become coincident with the audio decoding start time outputted from the DTSA register 24. The audio decoder 9 reads out the data from the audio code buffer 8 in response to the audio decoding start signal and starts its decoding. An audio signal generated as a result of such decoding is outputted to an unshown circuit.
The above is the operation performed when the transfer rate is a fixed one. FIG. 8 shows a timing chart of signals in the case of adopting a variable transfer rate. A high rate mode of 8 Mbps is selected in the operation before a time t3 and after a time t6, and a low rate mode of 2 Mbps is selected during a period between the times t3 and t6. The latter transfer rate is designated when the data are encoded by an unshown encoder.
In FIG. 8, a line D represents a state of writing the data in the video code buffer 6, and its inclination signifies a transfer rate. A line F represents a state of reading out the data from the video code buffer 6 by the video decoder 7. It follows, therefore, that the data within a shaded area in FIG. 8 is left in the video code buffer 6. The storage capacity of the video code buffer 6 is expressed by a distance perpendicular to the time axis extending from line D to a line E.
In the lower diagram of FIG. 8 (an enlarged view of the period from time t3 to time t6), a picture W is a subject to be noted now as an example. The data of the picture W begins to be loaded in the video code buffer 6 at the time t4, which is indicated by the timing data SCR affixed to the pack where the head G of the data of the picture W is stored. The data of the picture W begins to be decoded at a time t5, which is indicated by the timing data DTSV affixed to the packet where the head of the picture W is stored.
The input unit 29 is manipulated for instructing the control circuit 28 to start reproduction of the data from the picture W. The control circuit 8 sends a command to the drive 1, which then accesses a desired position on the optical disk incorporated therein and reproduces the recorded data. The reproduced data outputted from the drive 1 is supplied to the demodulator 2 so as to be demodulated, and the output therefrom is supplied to the ECC circuit 3 where a process of error detection and correction is executed. The data thus processed is supplied via the ring buffer 4 to the data separation circuit 21 in the data demultiplexer 5.
Data MUX.sub.-- RATE is disposed at the top of each pack, so that the transfer rate of the relevant pack can be detected by referring to this data. For example, the data separation circuit 21 controls the transfer rate in accordance with the value of this data. As to control of variable rate data, an exemplary description is disclosed in U.K. Patent GB 2 259 229 A (Date of publication: Mar. 3, 1993).
The data separation circuit 21 controlled by the control circuit 28 separates the video data from the output data of the ring buffer 4 and supplies the video data to the video code buffer 6. The circuit 21 further separates the timing data into SCR and DTSV, which are then supplied to the STC register 26 and the DTSV register 22 respectively and are stored therein. Since the operation of the audio section is similar to that mentioned above, a repeated description is omitted here.
The STC register 26 having stored the reference timing data SCR therein counts the clock pulses outputted from the clock generator 27 and increments the storage value in response to the clock pulses. The storage value of the STC register 26 is supplied as a system time clock (STC) signal to the comparators 23 and 25.
The timing data SCR corresponds to the time when demultiplexing is started after supply of the data of the picture W to the data demultiplexer 5. More specifically, it corresponds to a time t4 in the timing chart of FIG. 8. Therefore, the STC register 26 outputs the timing data (current time) from the time t4 to one input terminal of each of the comparators 23 and 25.
The DTSV register 22 supplies the video timing data DTSV, which indicates the picture-W decoding start time of the video decoder 7, to the other input terminal of the comparator 23. When the current time outputted from the STC register 26 has become coincident with the decoding start time outputted from the DTSV register 22 (i.e., at a time t5 in FIG. 8), the comparator 23 outputs a video decoding start signal to the video decoder 7. In response to the video decoding start signal thus received, the video decoder 7 reads out one frame of the video data written in the video code buffer 6 and then starts its decoding.
In the conventional demultiplexer of FIG. 5, as described, the time period from SCR (t4) to DTS (t5) is controlled by counting clock pulses of a fixed frequency, and the data are written in the buffer during such time period. Consequently, the data transfer rate is fixed at one value designated on the encoder side, so that it has been impossible heretofore to shorten the start-up delay even when the data supply rate to the demultiplexer 5 is lower than the maximum transfer rate and a margin thereof is still left.